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AIINFRA-007 backlog P1 curriculum pcie Effort XL

Extend PCIe fundamentals into accelerator discovery, initialization, isolation, telemetry, reset, firmware update, and failure recovery.

Depends on: AIINFRA-002

Outcome

A learner can follow a GPU, accelerator, NIC, or DPU from physical presence through enumeration and fleet readiness, then diagnose common cross-layer failures.

Deliverables

  • Reuse PCIe foundations already introduced in the NIC course.
  • Cover topology, switches, retimers, link training, enumeration, BARs, DMA, IOMMU, interrupts, error reporting, resets, and hot-plug.
  • Connect firmware ownership and update paths across the host, BMC, and device.
  • Add failure trees for missing, degraded, wedged, and mismatched devices.

Acceptance criteria

  • The track separates standardized PCIe mechanisms from platform-specific orchestration.
  • Each lifecycle phase names the responsible component and observable evidence.
  • At least one lab inspects a real or simulated PCIe topology and error state.
  • The material leads naturally into device attestation and fleet serviceability.